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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4510 BCD up/down counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
BCD up/down counter
FEATURES * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the "4510" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4510 are edge-triggered synchronous up/down BCD counters with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH
74HC/HCT4510
parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of all other input conditions.
Logic equation for terminal count: TC = CE . {(UP/DN) . Q . Q +(UP/DN) . Q 0 . Q 1 . Q 2 . Q 3 } 0 3 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 21 57 3.5 50 23 58 3.5 53 HCT ns MHz pF pF UNIT
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Philips Semiconductors
Product specification
BCD up/down counter
PIN DESCRIPTION PIN NO. 1 4, 12, 13, 3 5 6, 11, 14, 2 7 8 9 10 15 16 SYMBOL PL D0 to D3 CE Q0 to Q3 TC GND MR UP/DN CP VCC NAME AND FUNCTION parallel load input (active HIGH) parallel inputs count enable input (active LOW) parallel outputs terminal count output (active LOW) ground (0 V)
74HC/HCT4510
asynchronous master reset input (active HIGH) up/down control input clock input (LOW-to-HIGH, edge-triggered) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
BCD up/down counter
FUNCTION TABLE MR L L L L H Notes PL H L L L X UP/DN X X L H X
74HC/HCT4510
CE X H L L X
CP X X X
MODE parallel load no change count down count up reset
1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition
Fig.4 Functional diagram.
Fig.5 Timing diagram.
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Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Fig.6 Logic diagram.
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Philips Semiconductors
Product specification
BCD up/down counter
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay CP to Qn propagation delay MR to Qn propagation delay PL to Qn propagation delay CP to TC propagation delay CE to TC propagation delay MR to TC propagation delay PL to TC output transition time typ. 69 25 20 63 23 18 77 28 22 74 27 22 36 13 10 69 25 20 91 33 26 19 7 6 80 16 14 80 16 14 100 20 17 25 9 7 22 8 7 19 7 6 -40 to +85 max. min. 220 44 37 210 42 36 250 50 43 260 52 44 125 25 21 235 47 40 300 60 51 75 15 13 100 20 17 100 20 17 125 25 21 max. 275 55 47 265 53 45 315 63 54 325 65 55 155 31 26 295 59 50 375 75 64 95 19 16 120 24 20 120 24 20 150 30 26 -40 to +125 min. max. 330 66 56 315 63 54 375 75 64 395 78 66 190 38 32 355 71 60 450 90 77 110 22 19 ns
74HC/HCT4510
TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7
tPHL
ns
Fig.10
tPLH/ tPHL
ns
Fig.9
tPHL/ tPLH
ns
Fig.7
tPHL/ tPLH
ns
Fig.8
tPLH
ns
Fig.10
tPHL/ tPLH
ns
Fig.9
tTHL/ tTLH
ns
Fig.9
tW
pulse width CP, CE HIGH or LOW parallel load pulse width HIGH master reset pulse width HIGH
ns
Fig.7
tW
ns
Fig.10
tW
ns
Fig.10
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Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Tamb (C) 74HC SYMBOL PARAMETER +25 min. trem removal time MR to CP removal time PL to CP set-up time UP/DN to CP set-up time CE to CP set-up time Dn to PL hold time CE to CP hold time Dn to PL hold time UP/DN to CP 80 16 14 80 16 14 100 20 17 100 20 17 100 20 17 5 5 5 3 3 3 0 0 0 typ. 28 10 8 14 5 4 30 11 9 19 7 6 17 6 5 0 0 0 -6 -2 -2 -19 -7 -6 17 52 62 -40 to +85 max. min. 100 20 17 100 20 17 125 25 21 125 25 21 125 25 21 5 5 5 3 3 3 0 0 0 4.8 24 28 max. -40 to +125 min. 120 24 20 120 24 20 150 30 26 150 30 26 150 30 26 5 5 5 3 3 3 0 0 0 4.0 20 24 max. ns UNIT
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.10
trem
ns
Fig.10
tsu
ns
Fig.8
tsu
ns
Fig.8
tsu
ns
Fig.11
th
ns
Fig.8
th
ns
Fig.11
th
ns
Fig.8
fmax
maximum clock pulse 6.0 frequency 30 35
MHz
Fig.7
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Philips Semiconductors
Product specification
BCD up/down counter
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI
74HC/HCT4510
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below INPUT Dn PL, CE UP/DN CP MR UNIT LOAD COEFFICIENT 0.75 1.00 1.00 1.25 1.50
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tPHL tPLH/ tPHL tPHL/ tPLH tPHL/ tPLH tPLH tPHL/ tPLH tTHL/ tTLH tW tW propagation delay CP to Qn propagation delay MR to Qn propagation delay PL to Qn propagation delay CP to TC propagation delay CE to TC propagation delay MR to TC propagation delay PL to TC output transition time pulse width CP, CE HIGH or LOW parallel load pulse width HIGH master reset pulse width HIGH 16 16 typ. 27 25 28 29 17 31 35 7 9 6 -40 to +85 max. min. 50 42 53 58 31 50 68 15 20 20 max. 63 53 66 73 39 63 85 19 24 24 -40 to +125 min. max. 75 63 80 87 47 75 102 22 ns ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.10 Fig.9 Fig.7 Fig.8 Fig.10 Fig.10 Fig.9 Fig.7 Fig.10 UNIT VCC (V) WAVEFORMS TEST CONDITIONS
tW
20
4
25
30
ns
4.5
Fig.10
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Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Tamb (C) 74HCT SYMBOL PARAMETER +25 min. trem trem tsu tsu tsu th th th fmax removal time MR to CP removal time PL to CP set-up time UP/DN to CP set-up time CE to CP set-up time Dn to PL hold time CE to CP hold time Dn to PL hold time UP/DN to CP 23 17 20 20 20 5 5 0 typ. 13 10 12 6 6 0 0 -5 53 -40 to +85 max. min. 29 21 25 25 25 5 5 0 24 max. -40 to +125 min. 35 26 30 30 30 5 5 0 20 max. ns ns ns ns ns ns ns ns MHz UNIT
TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS
Fig.10 Fig.10 Fig.8 Fig.8 Fig.11 Fig.8 Fig.11 Fig.8 Fig.7
maximum clock pulse 30 frequency
AC WAVEFORMS
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Fig.7 Waveforms showing the clock (CP) to output (Qn) and terminal count (TC) propagation delays, the clock pulse width and the maximum clock pulse frequency.
Waveforms showing the set-up and hold times from count enable (CE) and up/down (UP/DN) control inputs to the clock pulse (CP), the propagation delays from UP/DN, CE to TC.
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Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9
Waveforms showing the preset enable pulse width, preset enable to output delays and output transition times.
Fig.10 Waveforms showing the master reset pulse, master reset to terminal count and Qn delay and master reset to clock removal time.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the data set-up and hold times to parallel load (PL).
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Philips Semiconductors
Product specification
BCD up/down counter
APPLICATION INFORMATION
74HC/HCT4510
Terminal count (TC) lines at the 2nd, 3rd, etc. stages may have a negative-going glitch pulse resulting from differential delays of different 4510s. These negative-going glitches do not affect proper 4510 operation. However, if the terminal count signals are used to trigger other edge sensitive logic devices, such as flip-flops or counters, the terminal count signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the UP/DN control is that the clock input to the first counting stage must be "HIGH". For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the CP input of the next stage with CE grounded.
Fig.13 Cascading counter packages (ripple clocking).
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Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Count-up mode: illegal states in BCD counters corrected in one count. Count-down mode: illegal states in BCD counters corrected in one or two counts. Count-up mode. Count-down mode.
Fig.14 State diagram.
Use the following formulae to calculate Ntotal: i = ( 10 x N i ) + N 0 1
N total
f in f out = ------------N total Formulae are only applicable if legal data is provided to the parallel inputs.
Fig.15 Programmable cascaded frequency divider.
PACKAGE OUTLINES parallel inputs D3 0 0 0 0 0 0 0 0 1 1 Note 1. no count; fout is HIGH. December 1990 12 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1 count-up n 9 8 7 6 5 4 3 2 1
(1)
count-down n
(1)
See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
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